This invention relates to an analogue current memory for storing input signals in the form of balanced sampled currents.
An analogue current memory comprising a first, coarse, current memory cell, a second, fine, current memory cell, an input for receiving a current to be stored, an output for delivering the stored current, first switch means for applying the input current to the first current memory cell during a first part of a first portion of a clock cycle, second switch means for applying the input current to the second current memory cell during a second part of the first portion of the clock cycle, and third switch means for delivering the combined output currents of the first and second current memory cells to the output of the current memory during a later portion of the clock cycle or during a subsequent clock cycle is disclosed in EP-A-0608 936, corresponding to U.S. Pat. No. 5,400,273 (PHB 33830). Two such current memories can be combined to produce a current memory suitable for storing balanced currents. While this current memory, which is known as S.sup.2 I current memory, gives a better performance than the simple current memory earlier proposed for switched current circuits and shown in FIG. 3.4 at page 36 of the book edited by C. Toumazou, J. B. Hughes, and N. C. Battersby entitled "SWITCHED-CURRENTS an analogue technique for digital technology" and published by Peter Peregrinus Limited in 1993, it still does not give an ideal performance.
In the operation of a switched-current memory, current transport errors are produced for a variety of reasons and these have been already described in the book edited by C. Toumazou et. al. referred to above. Briefly, they result from drain conductance of the memory transistors, drain-gate capacitance of the memory transistors and charge injection from the memory switches. These effects give the memory a current transport gain below its ideal value of unity. When used in integrators these non-ideal memories give a reduced Q-factor through the damping they introduce.
A variety of techniques have been employed to minimize these effects as described in the book referred to above and recently the S.sup.2 I technique was introduced. While the S.sup.2 I technique has proved highly effective in reducing errors, it has least impact on reducing errors arising from drain-gate capacitance. So, while reduction of drain-gate capacitance errors is important to all switched currents (SI) circuits, it is particularly so for the S.sup.2 I approach.